1 others n overview the DN8667NS is a semiconductor integrated circuit which incorporates a 8-bit shift register, a latch driver and a constant current driver to satisfy the demand for equal- ization of led panel brightness . it also incorporates the serial-in and serial-out/parallel-out functions . it employs the bi-cmos process : the 8-step shift register block and latch block consist of cmos while the 8-step parallel driver block is bipolar . n features serial-in, serial-out/parallel-out cascade connection possible constant current output (0 to 100 ma able to be set by one external resistor) output-forced on/off terminal attached (en) input/output cmos compatible n application led panel drive DN8667NS 8-bit shift register latch constant current driver ic 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 5.5 0.3 7.6 0.3 (0.4) 1.27 0.9 0.25 2.05 0.2 0.9 0.25 0.2 ?0.05 + 0.1 0.4 0.25 (0.4) 12.63 0.3 unit : mm 0.1 0.1 20-pin sop package (sop020-p-0300a) 12 8 constant current output gate latch shift register current set. data output gate control sig. latch control sig. data input clock input n block diagram constant current output constant current output shift register shift register external resistor
2 others DN8667NS parameter symbol rating unit n absolute maximum rating (ta = 25?c) * for printed board sm, it decreases with rate of 10.24 mw/?c from ta = 25 ?c. supply voltage output voltage output current power dissipation * operating ambient temperature storage temperature v cc v o i o p d t opr t stg 0 to + 7.0 0 to + 14 150 1.28 ?0 to + 85 ?5 to + 150 v v ma w ?c ?c n recommended operation range (ta=25 ?c) v cc operating supply voltage parameter symbol range 4.5v to 5.5v note) v cc = 5v unless otherwise specified. clk clk stb sin stb sin stb parameter symbol condition min typ max unit n electrical characteristics (v cc =5v,ta=25 2?c) input voltage positive direction negative direction 0.35v cc v t+ 0.7v cc v v sout = 0.1, v cc ?0.1v i sout = 20 a input current 0.2v cc 4.0 83 20 20 20 15 20 10 v t 0.55v cc v v 1h = 5.0v i ih ?25 25 a ma ma ma v 1l = 0v i il a a 25 v o = 14v (output off) i olk 2 ma 20 ma mh z ns 30 20 output voltage (sout) output current 1 (qn) output current 2 (qn) output current error between bits output leak current i oh = ?0.4ma v cc =5.5v v oh 0.5 i ol = 1.6ma v ol i ref = 0ma i cc1 i ref = ?.5ma input duty 40 to 60% i cc2 i ref = ?.5ma i cc3 f clk t w t su t h t r t f 100 117 v o (qn) = 0.5v i oi i oi 6 v cc = 5.0v, i ref = ?2ma v o (qn) = 1.0v di o v v % { i o (qn) = ?0 a, 90ma v o (qn) = 0.6v i ref = 2.5ma { total driver output off on supply current input pulse width clock frequency setting-up time holding time clock pulse rise time clock pulse fall time 500 500 ns ns ns ns ns ns ns v cc =5.0v r l =50 w c l =15pf
3 others DN8667NS symbol description n pin descriptions * calculation example v cc = 5v r rc = 910 w dgnd sin clk stb qn digital ground it is the serial data input terminal for shift register. the value of shift register shifts at the rising edge of clock input. pin no. pin name 1 2 3 4 5 digital ground serial data input clock input strobe input driver output 7,8 10,11 13,14 16 9,12 15 20 5 910 + 90 i o ( qn ) ? ** calculation example v cc = 5v i rc = 0.0025a i o ( qn ) ? 100ma 1 5 2 0.0025 r rc ? r rc ? 910 ( w ) ?80 v cc (v) 2 r rc ( w ) + 180 i rc ? (a) v cc (v) i rc (a) or r rc ? ( w ) ?80 20 v cc (v) r rc ( w ) + 90 i o ( qn ) ? (a) 1 2 setting the stb input to "h" forwards the data of shift register to the latch. when the stb input is set to "l" , even if the value of shift register changes, the value of latch is not changed. it outputs signals by using the polarity opposite to that of data taken into the latch. for example, when the value of serial input is "h" , the output becomes "l" level and the output is turned on. the output takes open collector form of npn transistor. output ground when the en input is set to "h" , all the outputs are turned off, independent of condition of shift register or latch driver. it is the terminal which performs the serial-output of data inputted from the sin. it connects the external resistor between rc and gnd and sets the current of output block. * output current calculation : ** rc terminal setting calculation : supply terminal 6 pgnd output ground 17 en enabling input 18 sout serial data output 19 rc constant current setting input 20 v cc v cc
4 others DN8667NS dq cp q d l q d l q d l q d l q d l DN8667NS sin v cc (20) dgnd (1) pgnd rc (19) v led current setting circuit led scan input gnd led sout (18) sin (2) clk (3) st b (4) en (17) q7 q3 q2 q1 q0 (16) (10) (8) (7) (5) logic input DN8667NS led panel block diagram n application circuit (6) (9) (12) (15) gnd led dq cp dq cp dq cp dq cp clk - - - stb h l en l l h sin q n q n q n q n sout q 6 q 6 q 6 nc q o q n nc h nc q m q m-1 nc h nc q 7 q 6 nc h nc input output n function table (note) h : high level, l : low level, : h or l q m , q n : h or l. however, for q n , "h"= off, "l"= on. - : shift from l to h, : shift from h to l nc : no change (note) 25 0 50 75 100 125 150 0 200 400 600 800 1000 1200 1400 1600 power dissipation p d (mw) ambient temperature ta (?c) p d ?ta glass epoxy printed board (50mm 50mm t0.8mm) rthj-a=97.7?c/w p d =1280 mw (25?c) single unit rthj-a=174.1?c/w p d = 718 mw (25?c) 1280 718 n characteristics curve
5 others DN8667NS 1.input timing 5v 0v 5v 0v 5v 0v clk sin stb 2.5v 2.5v t su(sin) t h(sin) t su(stb) 2.5v 2.5v t w(stb) (v il = 0v,v ih = 5.0v) (v il = 0v,v ih = 5.0v) 90% 90% 2.5v 2.5v 2.5v 2.5v 2.5v 2.transmission delay time 10% 10% t r(clk) t f(clk) t su(sin) t h(sin) 2.5v 2.5v t h(stb) 5v 0v 5v 0v voh vol qn en clk 2.5v 2.5v t plh 50% 50% 50% 50% t phl t phl t wh (clk) t wl(clk) 1/fclk n timing chart t plh
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